QCon is a practitioner-driven conference designed for technical team leads, architects, and project managers who influence software innovation in their teams.

Martin Thompson, High-Performance & Low-Latency Specialist at Real Logic / Track Host

Martin Thompson

Biography: Martin Thompson

Martin is a high-performance and low-latency specialist, with experience gained over two decades working with large scale transactional and big-data domains, including automotive, gaming, financial, mobile, and content management. He believes Mechanical Sympathy - applying an understanding of the hardware to the creation of software - is fundamental to delivering elegant, high-performance, solutions. Martin was the co-founder and CTO of LMAX, until he left to specialise in helping other people achieve great performance with their software. The Disruptor concurrent programming framework is just one example of what his mechanical sympathy has created. 

Twitter: @mjpt777
Video presentations: 4YOW! 2011: Martin Thompson - On Concurrent Programming and Concurrency Folklore

Presentation: Event Sourced Architectures and what we have forgotten about High-Availability

Track: Highly-available systems / Time: Wednesday 16:40 - 17:40 / Location: Fleming

The performance requirements of financial exchanges and high-frequency trading algorithms have driven all their designs to evolve, and nearly all these evolutions end up as variants of the event sourced design pattern. This pattern has proven to be one of the most successful when extreme transaction throughput at very low-latency are primary requirements, especially on highly-contended data. In addition, event sourced designs are perfectly deterministic which can be very useful when designing a highly-available solution.

Event sourcing is a relatively new term coined by Martin Fowler in 2005, however the techniques underlying it are routed in great technology going back to the 1970s in systems such as the Tandem NonStop. This talk will explore the benefits of event sourced designs as a basis for your architecture and shows how there are alternatives to suffering the curse that is now JEE.

The speaker will share two decades of his experience using event sourced designs and the benefits they have for supporting cross-cutting concerns such as high-availability, performance, security and auditing. These techniques have been applied across a range of domains including finance, insurance, mobile and automotive industries.

Presentation: Thursday Introduction

Track: Keynote / Time: Thursday 08:45 - 09:00 / Location: To be announced

Thursdays Track Hosts will present the program and provide a short introduction to the Tracks of the day

Presentation: Lock-free Algorithms for Ultimate Performance

Track: Finance / Time: Thursday 16:40 - 17:40 / Location: Henry Moore Room

In the challenge to reach the lowest possible latencies, as we push the boundaries of transaction processing, the good old fashioned lock imposes too much contention on our algorithms. This contention results in unpredictable latencies when we context switch into the kernel, and in addition limits throughput as Little’s law kicks in. Lock-free and wait-free algorithms can come to the rescue by side-stepping the issues of locks, and when done well can even avoid contention all together. However, lock-free techniques are not for the faint hearted. Programming with locks is hard. Programming using lock-free techniques is often considered the realm occupied only by technical wizards.

This session aims to take some of the fear out of non-locking techniques. Make no mistake this is not a subject for beginners but if you are brave, and enjoy understanding how memory and processors really work, then this session could open your eyes with what is possible if you are willing to dedicate the time and effort in this amazing subject area.

The attendees will learn the basics of how modern Intel x86_64 processors work and the memory model they implement that forms the foundations for lock-free programming. Empirical evidence will be presented to illustrate the raw throughput and potential latencies that can be achieved when using these techniques.